1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. Debug Checklist 8. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the GTS System PLL Clocks IP
3. Functional Description x
3.1. Architecture 3.2. Dynamic Reconfiguration Flow 3.3. Clocking and Reset Sequence 3.4. Timing Constraints 3.5. Operation Speed Switching 3.6. USXGMII 3.7. Fmax Requirement
3.1. Architecture x
3.1.1. 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) 3.1.2. 10M/100M/1G/2.5G/5G/10G (USXGMII) 3.1.3. 1G/2.5G/10G MGBASE PCS only
3.2. Dynamic Reconfiguration Flow x
3.2.1. RTL Generation using Dynamic Reconfiguration IP
3.2.1. RTL Generation using Dynamic Reconfiguration IP x
3.2.1.1. Step 1: Generating the 1G/2.5G/5G/10G Multirate Ethernet PHY IP 3.2.1.2. Step 2: QSF settings and Dynamic Reconfiguration (DR) profile assignments 3.2.1.3. Step 3: RTL Generation using Quartus® Prime Pro Edition Tool 3.2.1.4. Step 4: Instantiate the IP top file with the GTS Dynamic Reconfiguration Controller IP
3.3. Clocking and Reset Sequence x
3.3.1. Clocking 3.3.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration Controller Interface Signals
5.6. GMII Signals x
5.6.1. 1G/2.5G/10G MGBASE PCS Only PMA Interface
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
7. Debug Checklist x
7.1. Pre-Debugging Process 7.2. Clock Frequency 7.3. Recommended Reset Handling 7.4. Signals for Signal Tap
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. Debug Checklist
8. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version IP Version Changes
2025.04.07 25.1 6.0.0
  • Added support for Agilex™ 3 devices. Added the Agilex™ 3 devices information in the following topics:
    • Added Agilex™ 3 in the Device Family Support table.
    • Added Agilex™ 3 device information in the Slowest Device Speed Grade Support for Agilex™ 3 Devices table.
    • Updated the Reference and System PLL Clocks IP diagram.
  • Updated the Resource Utilization table with the following speed information:
    • 10M/100M/1G/2.5G (with 8-bit/16-bit adapter for HPS) with DR enabled
    • 10M/100M/1G/2.5G with DR enabled
    • 1G/2.5G with DR enabled
    • 10M/100M/1G/2.5G/5G/10G MGBASE PCS only with SGMII enabled
    • 1G/2.5G/10G (MGBASE) with IEEE 1588
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE 1588
  • Updated the description for the Adding the GTS System PLL Clocks IP topic.
  • Added dynamic reconfiguration information in the 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) topic.
  • Updated Architecture of the 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) Configuration diagram.
  • Added Dynamic Reconfiguration Flow topic.
  • Added a note in the Clocking topic about clocking limitation.
  • Added a note in the description for the Default transceiver mode parameter in the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core Parameters table.
  • Updated Analog Parameters Tab diagram.
  • Updated Interface Signal diagram to add o_refclk_bus_out signal.
  • Added o_refclk_bus_out to the GTS Reset Sequencer Signals table.
  • Added Dynamic Reconfiguration Controller Interface Signals topic.
2025.02.21 24.3.1 5.0.0 Updated the following diagrams:
  • Changed TX 64-bit GMII and RX 64-bit GMII to TX 64-bit XGMII and RX 64-bit XGMII in the Architecture of the 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) Configuration diagram.
  • Changed TX 16-bit GMII and RX 16-bit GMII to TX 32-bit XGMII and RX 32-bit XGMII in the Architecture of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration diagram.
2025.01.23 24.3.1 5.0.0
  • Updated 1G/2.5G/5G/10GMultirate Ethernet PHY Intel FPGA IP Core Features table to add information about PCS only mode.
  • Updated Supported Line-side Modes for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel FPGA IP for Agilex 5 Devices table to add information about MGBASE PCS only.
  • Updated Slowest Device Speed Grade Support table to add information about 1G/2.5G/10G MGBASE PCS only mode.
  • Updated Resource Utilization table to add information about 1G/2.5G/10G MGBASE PCS only.
  • Added information about 1G/2.5G/10G MGBASE PCS only configuration in the Architecture topic.
  • Added 1G/2.5G/10G MGBASE PCS Only Clocking figure in the Clocking topic.
  • Added information about MGBASE PCS only reset sequence in the Reset Sequence topic.
  • Added information about the 1G/2.5G/10G MGBASE PCS only and 10M/100M/1G/2.5G/10G MGBASE PCS only configurations in the Supported Operating Speed table.
  • Added information about the 1G/2.5G/10G MGBASE PCS only variant in the FmaxRequirement table.
  • Updated 1G/2.5G/5G/10GMultirate Ethernet PHY Intel FPGA IP Core Parameters table to include Ethernet Mode parameter.
  • Updated Interface Signals figure.
  • Updated Clock Signals table to include the following signals:
    • tx_coreclk_out
    • rx_coreclk_out
    • i_system_pll_clk_div2
    • tx_pma_clk
    • rx_pma_clk
  • Added 1G/2.5G/10G MGBASE PCS only configuration in the Clock Signals table for the following signals:
    • tx_clkout
    • rx_clkout
    • xgmii_tx_coreclkin
    • xgmii_rx_coreclkin
  • Added a note about the exception of the 1G/2.5G/10G MGBASE PCS only variant for the following signals in the Clock Signals table:
    • rx_cdr_refclk_p
    • i_system_pll_lock
    • rx_pma_clkout
    • o_clk_pll
  • Added a note in the Serial Interface Signals topic about the exception of the 1G/2.5G/10G MGBASE PCS only variant.
  • Added 1G/2.5G/10G MGBASE PCS only configuration in the XGMII Signals table and GMII Signals table.
  • Added 1G/2.5G/10G MGBASE PCS Only PMA Interface Signals topic.
  • Added 1G/2.5G/10G MGBASE PCS only configuration for the related signals in the Transceiver Mode table.
  • Added 1G/2.5G/10G MGBASE PCS only configuration for the related signals in the Operating Speed Signals table.
  • Added a note in the Transceiver Status and Reconfiguration Signals table about the exception of the 1G/2.5G/10G MGBASE PCS only variant.
  • Removed Dynamic Reconfiguration SRC Signals topic.
  • Added Debug Checklist topic.
2024.10.07 24.3 4.0.0
  • Removed the note about the Agilex™ 5 D-Series support in the About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices topic.
  • Updated 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Core Features table.
  • Updated Supported Line-side Modes for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices table.
  • Updated Slowest Device Speed Grade Support table.
  • Updated Resource Utilization table to add 10M/100M/1G/2.5G/5G/10G (MGBASE) and 1G/2.5G/10G (MGBASE) speed.
  • Updated Generated IP Files table to add aldec and xcelium.
  • Updated Architecture topic to update information about 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) and 10M/100M/1G/2.5G/5G/10G (USXGMII).
  • Updated Architecture of the 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) Configuration figure.
  • Updated Architecture of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Configuration figure.
  • Updated Clocking topic.
    • Updated Clocking Specifications table.
    • Updated figure title 2.5G, 1G/2.5G (MGBASE) Clocking to 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE).
    • Updated 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) Clocking figure.
    • Updated 10M/100M/1G/2.5G/5G/10G (NBASE) Clocking figure.
  • Updated Reset Sequence topic to add information about MGBASE and NBASE variants.
  • Updated NBASE and MGBASE 10G Reset Block Diagram.
  • Updated Timing Constraints table to include 1G/2.5G/10G (MGBASE) and 10M/100M/1G/2.5G/10G (MGBASE, SGMII) PHY configuration.
  • Updated Operating Speed Switching Methodology table:
    • Updated description for 1G/2.5G and 10M/100M/1G/2.5G PHY configuration.
    • Added 1G/2.5G/10G (MGBASE) and 10M/100M/1G/2.5G/10G (MGBASE) PHY configuration.
  • Updated Supported Operating Speed table to add information about 1G/2.5G/10G (MGBASE) and 10M/100M/1G/2.5G/10G (MGBASE).
  • Updated Fmax Requirement table to include 10M/100M/1G/2.5G/10G (MGBASE) default rate (10G) variant.
  • Updated 1G/2.5G/5G/10G Multirate Ethernet PHY Intel FPGA IP Core Parameters table to update the values for Speed parameter.
  • Added a note in the Analog Parameters topic.
  • Updated the PHY configurations and description columns in the Clock Signals table.
  • Updated the PHY configurations columns in the Reset Signals table.
  • Updated the signal names column in the Serial Interface Signals table.
  • Updated the width and description columns in the Avalon Memory-Mapped Interface Signals table.
  • Updated the width, description, and PHY configurations columns in the XGMII Signals table.
  • Updated the PHY configurations column in the GMII Signals table.
  • Updated the description and the PHY configurations columns in the PHY Status Signals table.
  • Updated the description and the PHY configurations columns in the Transceiver Mode and Operating Speed Signals table.
  • Updated the PHY configurations columns in the Dynamic Reconfiguration SRC Interface Signals table.
  • Updated Register Map Overview table.
2024.07.08 24.2 3.0.0
  • Added a note about Agilex™ 5 D-Series FPGAs and SoCs support in the About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 5 Devices topic.
  • Updated 1G/2.5G/5G/10G Multirate Ethernet PHY Interface with Agilex™ 5 Reference and System PLL Clocks IP figure in the Adding the Agilex 5 Reference and System PLL IP topic.
  • Added Analog Parameter topic.
  • Updated Interface Signals figure.
  • Updated description for latency_sclk signal in Clock Signals table.
  • Updated XGMII Signals table to add information about xgmii_tx_latency and xgmii_rx_latency signal.
  • Updated PHY Registers table to include PTP registers information.
2024.04.01 24.1 2.1.0 Initial public release.
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