1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813667
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices 2. Getting Started 3. Functional Description 4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP 5. Interface Signals 6. Configuration Registers 7. Debug Checklist 8. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices x
1.1. Release Information 1.2. Features 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization
2. Getting Started x
2.1. Introduction to Intel® FPGA IP 2.2. Installing and Licensing Intel® FPGA IPs 2.3. Specifying the IP Core Parameters and Options 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IPs 2.6. Integrating Your IP Core in Your Design
2.2. Installing and Licensing Intel® FPGA IPs x
2.2.1. Intel FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Adding the GTS System PLL Clocks IP
3. Functional Description x
3.1. Architecture 3.2. Dynamic Reconfiguration Flow 3.3. Clocking and Reset Sequence 3.4. Timing Constraints 3.5. Operation Speed Switching 3.6. USXGMII 3.7. Fmax Requirement
3.1. Architecture x
3.1.1. 2.5G, 1G/2.5G, 1G/2.5G/10G (MGBASE) 3.1.2. 10M/100M/1G/2.5G/5G/10G (USXGMII) 3.1.3. 1G/2.5G/10G MGBASE PCS only
3.2. Dynamic Reconfiguration Flow x
3.2.1. RTL Generation using Dynamic Reconfiguration IP
3.2.1. RTL Generation using Dynamic Reconfiguration IP x
3.2.1.1. Step 1: Generating the 1G/2.5G/5G/10G Multirate Ethernet PHY IP 3.2.1.2. Step 2: QSF settings and Dynamic Reconfiguration (DR) profile assignments 3.2.1.3. Step 3: RTL Generation using Quartus® Prime Pro Edition Tool 3.2.1.4. Step 4: Instantiate the IP top file with the GTS Dynamic Reconfiguration Controller IP
3.3. Clocking and Reset Sequence x
3.3.1. Clocking 3.3.2. Reset Sequence
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP x
4.1. Core Configuration 4.2. Analog Parameters
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. Serial Interface Signals 5.4. Avalon Memory-Mapped Interface Signals 5.5. XGMII Signals 5.6. GMII Signals 5.7. PHY Status Signals 5.8. Transceiver Mode and Operating Speed Signals 5.9. Transceiver Status and Reconfiguration Signals 5.10. GTS Reset Sequencer Signals 5.11. Dynamic Reconfiguration Controller Interface Signals
5.6. GMII Signals x
5.6.1. 1G/2.5G/10G MGBASE PCS Only PMA Interface
6. Configuration Registers x
6.1. Register Map 6.2. PHY Registers
7. Debug Checklist x
7.1. Pre-Debugging Process 7.2. Clock Frequency 7.3. Recommended Reset Handling 7.4. Signals for Signal Tap
1. About the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 Devices
2. Getting Started
3. Functional Description
4. Parameter Settings for 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP
5. Interface Signals
6. Configuration Registers
7. Debug Checklist
8. 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the 1G/2.5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

5.1. Clock Signals

Table 17.  Clock Signals
Signal Name Direction Width Description PHY Configurations
tx_clkout Output 1 GMII TX clock, derived from tx_pll_refclk. Provides 156.25 MHz timing reference for 2.5G; 62.5 MHz for 1G, 100M, and 10M.

For MGBASE PCS only variant, tx_clkout frequency is 156.25Mhz for 10G.

  • 2.5G
  • 1G/2.5G
  • 10M/100M/1G/2.5G
  • 1G/2.5G/10G (MGBASE)
  • 10M/100M/1G/2.5G/10G (MGBASE)
  • 1G/2.5G/10G MGBASE PCS only
rx_clkout Output 1 GMII RX clock, derived from tx_pll_refclk. Provides 156.25 MHz timing reference for 2.5G; 62.5 MHz for 1G, 100M, and 10M.

This clock is internally connected to tx_clkout with rate match FIFO.

For MGBASE PCS only variant, rx_clkout frequency is 156.25Mhz for 10G.

  • 2.5G
  • 1G/2.5G
  • 10M/100M/1G/2.5G
  • 1G/2.5G/10G (MGBASE)
  • 10M/100M/1G/2.5G/10G (MGBASE)
  • 1G/2.5G/10G MGBASE PCS only
csr_clk Input 1 Clock for the control and status interface. Altera recommends 100 MHz - 125 MHz for this clock. All MGBASE and NBASE variants
tx_coreclk_out Output 1 Drives the TX PMA interface (tx_parallel_data_out). This clock should be connected to the i_tx_coreclk of the GTS Transceiver PHY.

This clock is the same as the i_system_pll_clk_div2.

1G/2.5G/10G MGBASE PCS only
rx_coreclk_out Output 1 Drives the RX PMA interface (rx_parallel_data_out). This clock should be connected to the i_rx_coreclk of the GTS Transceiver PHY.

This clock is the same as the i_system_pll_clk_div2.

1G/2.5G/10G MGBASE PCS only
i_system_pll_clk_div2 Input 1

Clocks the GTS Transceiver PHY parallel interface. The frequency of this clock is the frequency of the system PLL of the GTS transceiver PHY divided by 2.

The minimum frequency of this clock should be ±100 PPM of 62.5 MHz for 10M/100M/1000M rates and 156.25 MHz for 2.5G and 10G rates.

1G/2.5G/10G MGBASE PCS only
tx_pma_clk Input 1 Input clock derived from the TX PLL reference clock (TX user clock) of the GTS Transceiver PHY. This clock is driving the GMII_16B interface.

The frequency of the clock is 62.5 MHz for 10M/100M/1000M rates and 156.25 MHz for 2.5G and 10G rates.

 1G/2.5G/10G MGBASE PCS only
rx_pma_clk Input 1

Input clock recovered from the RX serial line (RX user clock) of the GTS Transceiver PHY.

The frequency of the clock is 62.5 MHz for 10M/100M/1000M rates and 156.25 MHz for 2.5G and 10G rates.

 1G/2.5G/10G MGBASE PCS only
xgmii_tx_coreclkin Input 1 TX clock for XGMII logic before phase compensation FIFO.

Provides a 312.5 MHz timing reference for the 10M/100M/1G/2.5G/5G/10G (USXGMII) mode and 156.25 MHz timing reference for MGBASE 10G mode. This clock should be synchronous to o_clk_pll.

In MGBASE PCS only variant, this clock is synchronous to tx_clkout.

  • MGBASE variant:

    1G/2.5G/10G MGBASE PCS only

  • NBASE variant:

    10M/100M/1G/2.5G/5G/10G (USXGMII)
xgmii_rx_coreclkin Input 1 RX clock for XGMII logic after rate matcher.

Provides a 312.5 MHz timing reference for the 10M/100M/1G/2.5G/5G/10G (USXGMII) mode and 156.25 MHz timing reference for MGBASE 10G mode. This clock should be synchronous to o_clk_pll.

In MGBASE PCS only variant, this clock is synchronous to rx_clkout.

  • MGBASE variant:

    1G/2.5G/10G MGBASE PCS only

  • NBASE variant:

    10M/100M/1G/2.5G/5G/10G (USXGMII)

tx_pll_refclk_p

Input 1 Reference clock for each of the TX PLL.
  • MGBASE variant supports 156.25/312.5 MHz
  • NBASE variant supports 156.25/312.5/322.2656 MHz

rx_cdr_refclk_p

Input 1

Provides 156.25 MHz/312.5 MHz reference clock for the RX CDR.

 MGBASE variants only.
Note: Not available for 1G/2.5G/10G MGBASE PCS only variant.
i_system_pll_clk Input 1 To be connected to the GTS System PLL Clock Intel® FPGA IP PLL output.
  • NBASE variant supports 644.53125 MHz
  • MGBASE variant supports 322.2656 MHz
i_system_pll_lock Input 1 System PLL locked signal. All MGBASE and NBASE variants
Note: Not available for 1G/2.5G/10G MGBASE PCS only variant.
latency_measure_clk Input 1 Sampling clock for measuring the latency of the 16-bit GMII datapath. This clock operates at 80 MHz ± 100 ppm and is available only when the IEEE 1588 feature is enabled. MGBASE variants:
  • 2.5G
  • 1G/2.5G (MGBASE) with IEEE 1588 feature
latency_sclk Input 1 Sampling clock for measuring the latency of the transceiver AIB datapath. The clock period is 4.375 ns for 2.5G and 1G/2.5G (MGBASE), 6.5 ns for 10M/100M/1G/2.5G/5G/10G (USXGMII) It is available only when the IEEE 1588 feature is enabled.
  • MGBASE variants:

    1G and 2.5G with IEEE 1588

  • NBASE variants:

    10M/100M/1G/2.5G/5G/10G (USXGMII) with IEEE 1588
rx_pma_clkout Output 1 Recovered clock from CDR, operates at the following frequency:
10M/100M/1G/2.5G/5G/10G (USXGMII) speed mode:
  • All speeds: 156.25 MHz
Other speed modes:
  • 1G: 125 MHz
  • 2.5G: 312.5 MHz
  • 10G: 156.25 MHz
 All MGBASE and NBASE variants
Note: Not available for 1G/2.5G/10G MGBASE PCS only variant.
i_pma_cu_clk Input 1 PMA Control Unit clock, one per GTS bank for each side of the device. This clock port must be connected from the GTS Reset Sequencer Intel® FPGA IP. The clock frequency is 250 MHz. All MGBASE and NBASE variants
o_clk_pll Output 1 Clock derived from the System PLL associated with the Ethernet Port. The frequency is the system PLL frequency divided by 2. It should be used in the user logic to generate xgmii_*_coreclkin for a synchronous user application. NBASE variants: 10M/100M/1G/2.5G/5G/10G (USXGMII)
Note: Not available for 1G/2.5G/10G MGBASE PCS only variant.
i_clk_pll Input 1 This clock signal is unused. Tie this signal to ground. NBASE variants: 10M/100M/1G/2.5G/5G/10G (USXGMII)
gmii8b_tx_clkout Output 1 GMII TX clock, derived from tx_pll_refclk. Provides 312.5 MHz timing reference for 2.5G; 125 MHz for 1G, 100M, and 10M. GMII/MII transmit clock to HPS
gmii8b_rx_clkout Output 1 GMII RX clock, derived from tx_pll_refclk. Provides 312.5 MHz timing reference for 2.5G; 125 MHz for 1G, 100M, and 10M. GMII/MII receive clock to HPS
gmii8b_tx_clkin Input 1 TX out clock. GMII/MII transmit clock from HPS
Level Two Title