Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

ID 813665
Date 4/07/2025
Public

Visible to Intel only — GUID: nfa1438151340400

Ixiasoft

Document Table of Contents

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 25.1
IP Version 5.0.0

The Low Latency 10G Ethernet (LL 10GbE) MAC Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 devices provides the capability of generating design examples for selected configurations.

Figure 1. Development Stages for the Design Example