Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
ID
813665
Date
4/07/2025
Public
Visible to Intel only — GUID: nfa1438151340400
Ixiasoft
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature
6. 10G Ethernet Design Example
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Feature
9. Interface Signals Description
10. Configuration Registers Description
11. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
12. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
Visible to Intel only — GUID: nfa1438151340400
Ixiasoft
1. Quick Start Guide
Updated for: |
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Intel® Quartus® Prime Design Suite 25.1 |
IP Version 5.0.0 |
The Low Latency 10G Ethernet (LL 10GbE) MAC Intel® FPGA IP for Agilex™ 3 and Agilex™ 5 devices provides the capability of generating design examples for selected configurations.
Figure 1. Development Stages for the Design Example