Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

ID 813665
Date 4/07/2025
Public

Visible to Intel only — GUID: hze1724914245849

Ixiasoft

Document Table of Contents

4. 2.5G Ethernet Design Example

The 2.5G Ethernet design example demonstrates an Ethernet solution for Agilex™ 3 and Agilex™ 5 devices using the Low Latency Ethernet 10G MAC Intel® FPGA IP operating at 2.5G.

Generate the design example from the Example Design tab of the Low Latency Ethernet 10G MAC Intel® FPGA IP parameter editor.