Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10M/100M/1G Ethernet Design Example 3. 1G Ethernet Design Example with IEEE 1588v2 Feature 4. 2.5G Ethernet Design Example 5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature 6. 10G Ethernet Design Example 7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example 8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Feature 9. Interface Signals Description 10. Configuration Registers Description 11. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 12. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Signal Tap Debugging
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
1.5. Signal Tap Debugging x
1.5.1. Signal Tap Debug Signals
2. 10M/100M/1G Ethernet Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking Scheme 2.3.3. Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Procedure
3. 1G Ethernet Design Example with IEEE 1588v2 Feature x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
3.5. Hardware Testing x
3.5.1. Test Procedure
4. 2.5G Ethernet Design Example x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Hardware Testing 4.6. Interface Signals 4.7. Configuration Registers
4.3. Functional Description x
4.3.1. Design Components 4.3.2. Clocking Scheme 4.3.3. Reset Scheme
4.5. Hardware Testing x
4.5.1. Test Procedure
5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature x
5.1. Features 5.2. Hardware and Software Requirements 5.3. Functional Description 5.4. Simulation 5.5. Hardware Testing 5.6. Interface Signals 5.7. Configuration Registers
5.3. Functional Description x
5.3.1. Design Components 5.3.2. Clocking Scheme 5.3.3. Reset Scheme
5.4. Simulation x
5.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
5.5. Hardware Testing x
5.5.1. Test Procedure
6. 10G Ethernet Design Example x
6.1. Features 6.2. Hardware and Software Requirements 6.3. Functional Description 6.4. Simulation 6.5. Hardware Testing 6.6. Interface Signals 6.7. Configuration Registers
6.3. Functional Description x
6.3.1. Design Components 6.3.2. Clocking Scheme 6.3.3. Reset Scheme
6.5. Hardware Testing x
6.5.1. Test Procedure
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example x
7.1. Features 7.2. Hardware and Software Requirements 7.3. Functional Description 7.4. Simulation 7.5. Hardware Testing 7.6. Interface Signals 7.7. Configuration Registers
7.3. Functional Description x
7.3.1. Design Components 7.3.2. Clocking Scheme 7.3.3. Reset Scheme
7.5. Hardware Testing x
7.5.1. Test Procedure
8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Feature x
8.1. Features 8.2. Hardware and Software Requirements 8.3. Functional Description 8.4. Simulation 8.5. Hardware Testing 8.6. Interface Signals
8.3. Functional Description x
8.3.1. Design Components 8.3.2. Clocking Scheme 8.3.3. Reset Scheme
8.4. Simulation x
8.4.1. Test Case—Design Example with the IEEE 1588v2 Feature
8.5. Hardware Testing x
8.5.1. Test Procedure
9. Interface Signals Description x
9.1. Clock and Reset Interface Signals 9.2. Avalon® Memory-Mapped Interface Signals 9.3. Avalon® Streaming Interface Signals 9.4. PHY Interface Signals 9.5. Status Interface 9.6. IEEE 1588v2 Timestamp Interface Signals
10. Configuration Registers Description x
10.1. Register Access Definition 10.2. Low Latency Ethernet 10G MAC 10.3. PHY 10.4. Packet Generator and Traffic Monitor Register Map
10.3. PHY x
10.3.1. 1G/2.5G/5G/10G Multirate PHY
1. Quick Start Guide
2. 10M/100M/1G Ethernet Design Example
3. 1G Ethernet Design Example with IEEE 1588v2 Feature
4. 2.5G Ethernet Design Example
5. 2.5G Ethernet Design Example with IEEE 1588v2 Feature
6. 10G Ethernet Design Example
7. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example
8. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example with IEEE 1588 Feature
9. Interface Signals Description
10. Configuration Registers Description
11. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
12. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

10.4. Packet Generator and Traffic Monitor Register Map

Table 39.  Packet Generator Register Map
Byte Offset R/W Name Description HW Reset
0x00 RW NUMPKTS The total number of Ethernet packets that the traffic generator generates and transmits to the design components.

The width of this register is 32 bits.

 0
0x04 RW RANDOMLENGTH

Enables random packet length up to the value of the PKTLENGTH register.

  • 0x00: Fixed length.
  • 0x01: Random length.
 0
0x08 RW RANDOMPAYLOAD

Enables random contents of the payload.

  • 0x00: Incremental.
  • 0x01: Random.
 0
0x0C RW START Start the generation of the Ethernet traffic by writing 0x01 to this register. 0
0x10 RW STOP Stops the generation of the Ethernet traffic by writing 0x01 to this register. 0
0x14 RW MACSA0 The lower 32 bits of the source address. 0
0x18 RW MACSA1 The upper 16 bits of the source address. The remaining 16 bits are not used. 0
0x1C RW MACDA0 The lower 32 bits of the destination address. 0
0x20 RW MACDA1 The upper 16 bits of the source address. The remaining 16 bits are not used. 0
0x24 RO TXPKTCNT The number of packets that the traffic generator transmitted. Read this register when the traffic generator is not active, for example, when the testing has completed. 0
0x34 RW PKTLENGTH When random-sized packets are enabled, this register specifies the maximum payload length. Otherwise, it specifies the length of the packet to be generated.

The width of this register is 14 bits.

 0
Table 40.  Traffic Monitor Register Map
Byte Offset R/W Name Description HW Reset
0x00 RW RXPKTCNT_EXPT The number of packets that the traffic monitor expects to receive. 0xFFFFFFFF
0x04 RO RXPKTCNT_GOOD The number of good packets received by the traffic monitor. 0
0x08 RO RXPKTCNT_BAD The number of packets received with CRC error. 0
0x0C RO RXBYTECNT_LO32 The lower 32 bits of the counter that keeps track of the total number of bytes the traffic monitor received. 0
0x10 RO RXBYTECNT_HI32 The upper 32 bits of the counter that keeps track of the total number of bytes the traffic monitor received. 0
0x14 RO RXCYCLCNT_LO32 The lower 32-bit of the counter that keeps track of the total number of clock cycles required by the traffic monitor to receive the expected number of packets. 0
0x18 RO RXCYCLCNT_HI32 The upper 32-bit of the counter that keeps track of the total number of clock cycles required by the traffic monitor to receive the expected number of packets. 0
0x1C RW RXCTRL_STATUS

Monitors the configuration and status register.

  • Bit [0]: Set to 1 to initialize all of the traffic monitor counters.
  • Bit [1]: Reserved.
  • Bit [2]: When set to 1, indicates that the traffic monitor has received the total number of expected packets. This bit is a read-only bit.
  • Bits [31:3]: Reserved.
 0
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