Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
Visible to Intel only — GUID: nfh1487227815158
Ixiasoft
Visible to Intel only — GUID: nfh1487227815158
Ixiasoft
2. 10M/100M/1G Ethernet Design Example
The 10M/100M/1G Ethernet design example demonstrates an Ethernet solution for Agilex™ 3 and Agilex™ 5 devices using the Low Latency Ethernet 10G MAC Intel® FPGA IP operating at 10M, 100M, and 1G.
Generate the design example from the Example Design tab of the Low Latency Ethernet 10G MAC Intel® FPGA IP parameter editor.