AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

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ID 776775
Date 4/23/2025
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1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs x
1.1. AC Coupling and DC Coupling 1.2. TDS I/O On-Chip Termination 1.3. TDS I/O External Termination 1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers 1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver 1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver 1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver 1.8. Summary 1.9. Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1.1. AC Coupling and DC Coupling x
1.1.1. Capacitors and Components Selection
1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers x
1.4.1. Schematic Topology for Transmitter and Receiver Buffers 1.4.2. Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver x
1.5.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.2. Reduced VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.3. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Series Resistors 1.5.4. LVDS Transmitter Interfaces with 1.2 V TDS Receiver 1.5.5. LVDS Transmitter Interfaces with 1.2 V TDS Receiver and Series Resistors 1.5.6. LVDS Transmitter Interfaces with 1.1 V TDS Receiver and Series Resistors 1.5.7. LVDS Transmitter Interfaces with 1.05 V TDS Receiver and Series Resistors
1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver x
1.6.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.6.2. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Single Attenuation Resistor 1.6.3. Minimum VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver
1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver x
1.7.1. DC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver 1.7.2. AC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers

In this application note, the Agilex™ 7 M-Series FPGA interfaces with the Arria® 10 and Cyclone® V FPGAs. The Arria® 10 and Cyclone® V FPGAs represent a device that supports the listed ANSI/TIA/EIA-644-compliant I/O standards.
Table 3.  Differential Signaling and I/O Standards— Arria® 10 Specifications
Voltages (V) I/O Standard
LVDS RSDS Mini-LVDS LVPECL
VCCIO Min. 1.71 1.71 1.71 1.71
Typ. 1.8 1.8 1.8 1.8
Max. 1.89 1.89 1.89 1.89
VID Min. 0.1 0.1 0.2 0.3
Cond. VCM = 1.25 V VCM = 1.25 V — —
Max. — — 0.6 —
VICM(DC) Min. 0 1 0.3 0.4 0.6 1
Cond.

Data rate ≤ 700 Mbps

Data rate > 700 Mbps

 — —

Data rate ≤ 700 Mbps

Data rate > 700 Mbps
Max. 1.85 1.6 1.4 1.325 1.7 1.6
VOD Min. 0.247 0.1 0.25 —
Typ. — 0.2 — —
Max. 0.6 0.6 0.6 —
VOCM Min. 1.125 0.5 1 —
Typ. 1.25 1.2 1.2 —
Max. 1.375 1.4 1.4 —
Table 4.  Differential Signaling and I/O Standards— Cyclone® V Specifications
Voltages (V) I/O Standard
LVDS RSDS Mini-LVDS LVPECL
VCCIO Min. 2.375 2.375 2.375 2.375
Typ. 2.5 2.5 2.5 2.5
Max. 2.625 2.625 2.625 2.625
VID Min. 0.1 0.1 0.2 0.3
Cond. VCM = 1.25 V VCM = 1.25 V — —
Max. — — 0.6 —
VICM(DC) Min. 0.05 1.05 0.25 0.3 0.6 1
Cond.

Data rate ≤ 700 Mbps

Data rate ≥ 700 Mbps

 — —

Data rate ≤ 700 Mbps

Data rate ≥ 700 Mbps
Max. 1.80 1.55 1.45 1.425 1.8 1.6
VOD Min. 0.247 0.1 0.25 —
Typ. — 0.2 — —
Max. 0.6 0.6 0.6 —
VOCM Min. 1.125 0.5 1 —
Typ. 1.25 1.2 1.2 —
Max. 1.375 1.4 1.4 —

Section Content
Schematic Topology for Transmitter and Receiver Buffers
Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL

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