AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

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ID 776775
Date 4/23/2025
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Document Table of Contents
Document Table of Contents x
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs x
1.1. AC Coupling and DC Coupling 1.2. TDS I/O On-Chip Termination 1.3. TDS I/O External Termination 1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers 1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver 1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver 1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver 1.8. Summary 1.9. Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1.1. AC Coupling and DC Coupling x
1.1.1. Capacitors and Components Selection
1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers x
1.4.1. Schematic Topology for Transmitter and Receiver Buffers 1.4.2. Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver x
1.5.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.2. Reduced VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.3. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Series Resistors 1.5.4. LVDS Transmitter Interfaces with 1.2 V TDS Receiver 1.5.5. LVDS Transmitter Interfaces with 1.2 V TDS Receiver and Series Resistors 1.5.6. LVDS Transmitter Interfaces with 1.1 V TDS Receiver and Series Resistors 1.5.7. LVDS Transmitter Interfaces with 1.05 V TDS Receiver and Series Resistors
1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver x
1.6.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.6.2. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Single Attenuation Resistor 1.6.3. Minimum VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver
1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver x
1.7.1. DC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver 1.7.2. AC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

1.4.2. Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL

These recommended topologies are based on data sheet specifications.
Note: In your design, ensure that you meet the VID, VICM, and maximum input voltage specifications of the TDS device ( Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs).
Figure 1. AC-Coupled LVDS, RSDS, or Mini-LVDS Transmitter Interface to FPGA TDS ReceiverIn this figure, the ANSI/TIA/EIA-644-compliant transmitter is the Arria® 10 or Cyclone® V FPGA while the TDS receiver is the Agilex™ 7 M-Series, Agilex™ 5, or Agilex™ 3 FPGA.
Figure 2. FPGA 1.3 V TDS Transmitter Interface to LVDS or LVPECL Receiver—Data Rate ≤ 700 MbpsIn this figure, the TDS transmitter is the Agilex™ 7 M-Series, Agilex™ 5, or Agilex™ 3 FPGA while the ANSI/TIA/EIA-644-compliant receiver is the Arria® 10 or Cyclone® V FPGA. This figure is for data rate ≤ 700 Mbps.


Figure 3. FPGA 1.3 V TDS Transmitter Interface to LVDS or LVPECL Receiver—Data Rate > 700 MbpsIn this figure, the TDS transmitter is the Agilex™ 7 M-Series, Agilex™ 5, or Agilex™ 3 FPGA while the ANSI/TIA/EIA-644-compliant receiver is the Arria® 10 or Cyclone® V FPGA. This figure is for data rate > 700 Mbps.
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