AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

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ID 776775
Date 4/23/2025
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Document Table of Contents
Document Table of Contents x
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs x
1.1. AC Coupling and DC Coupling 1.2. TDS I/O On-Chip Termination 1.3. TDS I/O External Termination 1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers 1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver 1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver 1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver 1.8. Summary 1.9. Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1.1. AC Coupling and DC Coupling x
1.1.1. Capacitors and Components Selection
1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers x
1.4.1. Schematic Topology for Transmitter and Receiver Buffers 1.4.2. Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver x
1.5.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.2. Reduced VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.3. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Series Resistors 1.5.4. LVDS Transmitter Interfaces with 1.2 V TDS Receiver 1.5.5. LVDS Transmitter Interfaces with 1.2 V TDS Receiver and Series Resistors 1.5.6. LVDS Transmitter Interfaces with 1.1 V TDS Receiver and Series Resistors 1.5.7. LVDS Transmitter Interfaces with 1.05 V TDS Receiver and Series Resistors
1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver x
1.6.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.6.2. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Single Attenuation Resistor 1.6.3. Minimum VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver
1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver x
1.7.1. DC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver 1.7.2. AC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver

In the following receiver simulations, the ANSI/TIA/EIA-644-compliant LVDS transmitter is the Arria® 10 FPGA. The TDS receiver is the Agilex™ 7 M-Series FPGA.
Table 5.  Simulation Conditions
Item Conditions
Simulator Siemens* HyperLynx LineSim VX.2.11_Update2 build 20026110
Transmitter Arria® 10 FPGA LVDS buffer
Receiver Agilex™ 7 M-Series FPGA 1.05 V, 1.1 V, 1.2 V, and 1.3 V V TDS buffers3
Data Rate 600 Mbps, 1600 Mbps
Encoding 8b/10b with 10-bit order
Measurement At the far end receiver

Section Content
LVDS Transmitter Interfaces with 1.3 V TDS Receiver
Reduced VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver
LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Series Resistors
LVDS Transmitter Interfaces with 1.2 V TDS Receiver
LVDS Transmitter Interfaces with 1.2 V TDS Receiver and Series Resistors
LVDS Transmitter Interfaces with 1.1 V TDS Receiver and Series Resistors
LVDS Transmitter Interfaces with 1.05 V TDS Receiver and Series Resistors

3 The Agilex™ 7 M-Series FPGA TDS buffers are generated from the Quartus® Prime EDA Netlist Writer GUI version 24.3 with the Enable per pin RLC package model with mutual coupling setting enabled. For more information about generating custom IBIS models with the EDA Netlist Writer GUI, refer to the Quartus® Prime Pro Edition User Guide: PCB Design Tools .
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