AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

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ID 776775
Date 4/23/2025
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Document Table of Contents
Document Table of Contents x
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs x
1.1. AC Coupling and DC Coupling 1.2. TDS I/O On-Chip Termination 1.3. TDS I/O External Termination 1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers 1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver 1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver 1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver 1.8. Summary 1.9. Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1.1. AC Coupling and DC Coupling x
1.1.1. Capacitors and Components Selection
1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers x
1.4.1. Schematic Topology for Transmitter and Receiver Buffers 1.4.2. Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver x
1.5.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.2. Reduced VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.3. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Series Resistors Simulation Results 1.5.4. LVDS Transmitter Interfaces with 1.2 V TDS Receiver 1.5.5. LVDS Transmitter Interfaces with 1.2 V TDS Receiver and Series Resistors 1.5.6. LVDS Transmitter Interfaces with 1.1 V TDS Receiver and Series Resistors 1.5.7. LVDS Transmitter Interfaces with 1.05 V TDS Receiver and Series Resistors
1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver x
1.6.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.6.2. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Single Attenuation Resistor 1.6.3. Minimum VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver
1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver x
1.7.1. DC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver 1.7.2. AC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

1.5.3. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Series Resistors

If the LVDS transmitter does not support programmable VOD and the TDS receiver specifications are violated as shown in the LVDS Transmitter Interfaces with 1.3 V TDS Receiver at 600 Mbps figure, additional passive circuitry can be added to further reduce the differential voltage swing.

Series resistors can be used to reduce the differential voltage swing when either the maximum input voltage or maximum VID is violated at the TDS receiver. The resistor values can be adjusted to accommodate specific board designs and all process, voltage, and temperature (PVT) conditions.

Figure 9. Simulation Topology (1.3 V TDS Receiver) With Series Resistors
Note: The DC bias circuitry uses two 50-Ω resistors to VICM. This is considered a high current biasing circuit which requires the RD OCT resistor to be disabled.

Simulation Results

Figure 10. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Series Resistors at 600 Mbps
Note:
  1. The waveform shows the VICM is within the acceptable range of the 1.3 V TDS receiver, which is between 500 mV and 1.2 V when not using RD OCT.
  2. The waveform shows a maximum input voltage of 1.1 V when considering the overshoot, which meets the maximum input voltage limit for this case, 1.427 V.
  3. The waveform shows the VID has been reduced by the series resistors and the waveform meets both the maximum VID (454 mV) and minimum VID (100 mV) specifications of the 1.3 V TDS receiver.
Figure 11. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Series Resistors at 1600 Mbps
Note: This case again demonstrates the use of source series resistors can meet the 1.3 V TDS receiver specifications, up to the maximum supported data rate of 1600 Mbps.
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