AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

Download PDF
ID 776775
Date 4/23/2025
Public
Document Table of Contents
Document Table of Contents x
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs x
1.1. AC Coupling and DC Coupling 1.2. TDS I/O On-Chip Termination 1.3. TDS I/O External Termination 1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers 1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver 1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver 1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver 1.8. Summary 1.9. Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1.1. AC Coupling and DC Coupling x
1.1.1. Capacitors and Components Selection
1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers x
1.4.1. Schematic Topology for Transmitter and Receiver Buffers 1.4.2. Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver x
1.5.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.2. Reduced VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.3. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Series Resistors 1.5.4. LVDS Transmitter Interfaces with 1.2 V TDS Receiver 1.5.5. LVDS Transmitter Interfaces with 1.2 V TDS Receiver and Series Resistors 1.5.6. LVDS Transmitter Interfaces with 1.1 V TDS Receiver and Series Resistors 1.5.7. LVDS Transmitter Interfaces with 1.05 V TDS Receiver and Series Resistors
1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver x
1.6.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.6.2. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Single Attenuation Resistor 1.6.3. Minimum VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver
1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver x
1.7.1. DC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver 1.7.2. AC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver Simulation Results
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

1.7.2. AC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver

The Arria® 10 FPGA LVDS receiver specifications require a reduced common mode range (1.0 V to 1.6 V) and lower maximum input voltage (1.6 V) for data rates above 700 Mbps. As seen in the DC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver—600 Mbps figure, the common mode voltage of 1.0 V has no margin for variation tolerance for data rates above 700 Mbps, so AC coupling with DC bias circuitry would be required, as shown in the following simulation.

Figure 28. Simulation Topology (AC Coupled)—Data Rate > 700 Mbps (1600 Mbps)


Simulation Results

Figure 29. AC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver at 1600 Mbps
Note:
  1. The waveform shows the VICM is within the acceptable range of the LVDS receiver, which is between 1 V and 1.6 V for data rates above 700 Mbps.
  2. The waveform shows a maximum input voltage of less than 1.5 V when considering the overshoot, which meets the maximum input voltage limit of 1.6 V for data rates above 700 Mbps.
  3. The Arria® 10 FPGA LVDS receiver does not have a maximum VID specification. The minimum VID is 200 mV, which meets the LVDS receiver’s minimum VID requirement of 100 mV.
  4. This case demonstrates that AC coupling with DC bias circuitry is sufficient to meet the Arria® 10 FPGA LVDS receiver requirements at the maximum supported data rate of 1600 Mbps.
Level Two Title