AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

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ID 776775
Date 4/23/2025
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Document Table of Contents x
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs x
1.1. AC Coupling and DC Coupling 1.2. TDS I/O On-Chip Termination 1.3. TDS I/O External Termination 1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers 1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver 1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver 1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver 1.8. Summary 1.9. Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1.1. AC Coupling and DC Coupling x
1.1.1. Capacitors and Components Selection
1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers x
1.4.1. Schematic Topology for Transmitter and Receiver Buffers 1.4.2. Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver x
1.5.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.2. Reduced VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.3. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Series Resistors 1.5.4. LVDS Transmitter Interfaces with 1.2 V TDS Receiver Simulation Results 1.5.5. LVDS Transmitter Interfaces with 1.2 V TDS Receiver and Series Resistors 1.5.6. LVDS Transmitter Interfaces with 1.1 V TDS Receiver and Series Resistors 1.5.7. LVDS Transmitter Interfaces with 1.05 V TDS Receiver and Series Resistors
1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver x
1.6.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.6.2. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Single Attenuation Resistor 1.6.3. Minimum VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver
1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver x
1.7.1. DC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver 1.7.2. AC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

1.5.4. LVDS Transmitter Interfaces with 1.2 V TDS Receiver

The TDS receiver can also be supported using 1.2 V, 1.1 V, and 1.05 V. The VID, VICM, and maximum input voltage specifications are identical when using these I/O bank voltages.

The following simulations use the Arria® 10 FPGA LVDS transmitter with a high programmable VOD setting to interface with the Agilex™ 7 M-Series FPGA 1.2 V, 1.1 V, and 1.05 V TDS receivers.

Figure 12. Simulation Topology (1.2 V TDS Receiver)
Note: The DC bias circuitry uses two 50-Ω resistors to VICM. This is considered a high current biasing circuit which requires the RD OCT resistor to be disabled.

Simulation Results

Figure 13. LVDS Transmitter Interfaces with 1.2 V TDS Receiver at 600 Mbps
Note:
  1. The waveform shows the VICM is within the acceptable range of the 1.2 V TDS receiver, which is between 800 mV and 950 mV.
  2. The waveform shows a maximum input voltage greater than 1.17 V when considering the overshoot, which exceeds the maximum input voltage limit for this case (1.17 V), resulting in a violation. The limit is derived from the VICM (max) + VID (max)/2 equation, where:
    1. VICM (max) is 0.95 V
    2. VID (max) is 0.454 V
  3. The waveform shows VID exceeds 500 mV when considering the overshoot, which violates the maximum VID of the 1.2 V TDS receiver (454 mV).
  4. You can add series resistors between the LVDS transmitter and the AC coupling capacitors to reduce the differential voltage swing for this case.
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