AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

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ID 776775
Date 4/23/2025
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Document Table of Contents
Document Table of Contents x
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs x
1.1. AC Coupling and DC Coupling 1.2. TDS I/O On-Chip Termination 1.3. TDS I/O External Termination 1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers 1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver 1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver 1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver 1.8. Summary 1.9. Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
1.1. AC Coupling and DC Coupling x
1.1.1. Capacitors and Components Selection
1.4. Termination and Biasing Schemes for TDS Transmitters and Receivers x
1.4.1. Schematic Topology for Transmitter and Receiver Buffers 1.4.2. Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
1.5. Simulation: Arria® 10 FPGA as LVDS Transmitter and Agilex™ 7 M-Series FPGA as TDS Receiver x
1.5.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.2. Reduced VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.5.3. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Series Resistors 1.5.4. LVDS Transmitter Interfaces with 1.2 V TDS Receiver 1.5.5. LVDS Transmitter Interfaces with 1.2 V TDS Receiver and Series Resistors 1.5.6. LVDS Transmitter Interfaces with 1.1 V TDS Receiver and Series Resistors 1.5.7. LVDS Transmitter Interfaces with 1.05 V TDS Receiver and Series Resistors
1.6. Simulation: Cyclone® V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver x
1.6.1. LVDS Transmitter Interfaces with 1.3 V TDS Receiver 1.6.2. LVDS Transmitter Interfaces with 1.3 V TDS Receiver and Single Attenuation Resistor 1.6.3. Minimum VOD LVDS Transmitter Interfaces with 1.3 V TDS Receiver
1.7. Simulation: Agilex™ 7 M-Series FPGA as TDS Transmitter and Arria® 10 as LVDS Receiver x
1.7.1. DC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver 1.7.2. AC Coupled 1.3 V TDS Transmitter Interfaces with LVDS Receiver
1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

1. True Differential Signaling Termination and Biasing for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs

Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs use the True Differential Signaling (TDS) I/O standard to interface with differential signaling I/O standards. The TDS transmitters and receivers, with AC or DC coupling configurations, require different termination and biasing schemes for different I/O standards.

This application note demonstrates the recommended termination and biasing by interfacing an Agilex™ 7 M-Series FPGA with the Arria® 10 and Cyclone® V FPGAs. The Arria® 10 and Cyclone® V FPGAs represent a device that supports ANSI/TIA/EIA-644-compliant LVDS, RSDS, mini-LVDS, and LVPECL I/O standards.

Table 1.  Differential Signaling Interfaces Supported by TDS
Interface Application
LVDS General applications
RSDS Flat panel display
Mini-LVDS TFT LCD panel column driver
LVPECL Video graphics and clock distribution
Table 2.  TDS I/O Standards for Agilex™ 7 M-Series, Agilex™ 5, and Agilex™ 3 FPGAs
I/O Standard Direction Voltages (V)
VID VICM(DC) VOD VOCM
Min. Max. Min. Max. Min. Max. Min. Typ. Max.
1.3 V TDS 2

Transmit

Receive

 0.1 0.454 0.5 1.375

1

0.247 0.454 0.9 1.0 1.1
1.2 V TDS2 Receive 0.1 0.454 0.8 0.95 — — — — —
1.1 V TDS2 Receive 0.1 0.454 0.8 0.95 — — — — —
1.05 V TDS2 Receive 0.1 0.454 0.8 0.95 — — — — —

Section Content
AC Coupling and DC Coupling
TDS I/O On-Chip Termination
TDS I/O External Termination
Termination and Biasing Schemes for TDS Transmitters and Receivers
Simulation: Arria 10 FPGA as LVDS Transmitter and Agilex 7 M-Series FPGA as TDS Receiver
Simulation: Cyclone V FPGA as LVDS Transmitter and M-Series FPGA as TDS Receiver
Simulation: Agilex 7 M-Series FPGA as TDS Transmitter and Arria 10 as LVDS Receiver
Summary
Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Agilex 7 M-Series, Agilex 5, and Agilex 3 FPGAs

Related Information
1 The VICM(DC) voltage must not exceed 1.2 V if you disable on-chip differential termination (RD OCT) to use external on-board termination.
2 The maximum input voltage driven into the True Differential Signaling input buffer must not exceed VICM(max) + VID(max)/2.
Level Two Title