High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 7/14/2023

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5.4. Platform Designer-Only Interface

The HBM2E IP in the Platform Designer includes additional target NoC interfaces not present in the generated synthesis fileset. These are a special type of interface without associated signals, which provide a connection point that you can use to specify the routing of traffic between NoC initiators and targets. You can use the Platform Designer to connect a NoC initiator instantiated by the NoC initiator IP to one or more NoC targets instantiated within the HBM2E IP.

The number of HBM2E target NoC interfaces available in the Platform Designer is determined by the number of channels enabled on the HBM2E IP. Each pseudo-channel has dedicated NoC target hardware, and that NoC target includes a target NoC interface that features in the Platform Designer patch panel. The HBM2E IP exposes a target NoC interface for each AXI-Lite NoC target bridge enabled by the IP. These NoC targets provide access to control and status registers of a predefined pair of HBM2E channels. The naming convention for HBM2E pseudo-channel target NoC interfaces follows the pattern of t_ch<x>_u<y>_axi4noc, where x is the channel number and y is the pseudo-channel number. The HBM2E controller register access target NoC interface naming is t_ch<z>_ch<z+1>_sb_axi4noc, where z is 0, 2, 4 or 6.

Note: For more information on the NoC Initiator, refer to the Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide .