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1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance
7. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
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5.2.5. AXI4-Lite Interface
The AXI4-Lite interface allows access to the high-bandwidth memory controller's control and status registers. The AXI4-Lite interface is intended primarily for use in relatively low bandwidth sideband operations.
Port Name | Width | Direction | Description |
---|---|---|---|
sb_awaddr | 27 | Input | Write Address. Target address of the AXI4-Lite write command. |
sb_awvalid | 1 | Input | Write Address Valid. This signal indicates that valid write address information is available. |
sb_awready | 1 | Output | Write Address Channel Ready. This signal indicates that the slave is ready to accept a write command. |
sb_awprot | 3 | Input | Protection Type. [Reserved for Future Use]. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. |
Port Name | Width | Direction | Description |
---|---|---|---|
sb_wdata | 32 | Input | Write Data. |
sb_wstrb | 4 | Input | Write Strobes (Byte Enables). This signal indicates which byte lanes (for sb_wdata) hold valid data. There is one write strobe bit for each eight bits of the write data bus. |
sb_wvalid | 1 | Input | Write Valid. This signal indicates that valid write data and strobes are available. |
sb_wready | 1 | Output | Write Ready. This signal indicates that the slave (HBM controller) can accept the write data. |
Port Name | Width | Direction | Description | ||||||
---|---|---|---|---|---|---|---|---|---|
sb_bresp | 2 | Output | Write Response. This signal indicates the result of the most recent write command.
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sb_bvalid | 1 | Output | Write Response Valid. This signal indicates that a valid write response is available. | ||||||
sb_bready | 1 | Input | Response Ready. This signal indicates that the master can accept a write response. |
Port Name | Width | Direction | Description |
---|---|---|---|
sb_araddr | 27 | Input | Read Address. Target address of the AXI4-Lite read command. |
sb_arvalid | 1 | Input | Read Address Valid. This signal indicates that a valid read address is available. |
sb_arready | 1 | Output | Read Address Ready. This signal indicates that the slave is ready to accept a read command. |
sb_arprot | 3 | Input | Protection Type. [Reserved for Future Use]. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. |
Port Name | Width | Direction | Description | ||||||
---|---|---|---|---|---|---|---|---|---|
sb_rdata | 32 | Output | Read Data. | ||||||
sb_rresp | 2 | Output | Read Response. This signal indicates the result of the most recent read command.
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sb_rvalid | 1 | Output | Read Valid. This signal indicates that a valid read response is available. | ||||||
sb_rready | 1 | Input | Read Ready. This signal indicates that the master can accept the read data and response information. |