High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 7/14/2023

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Document Table of Contents

7. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.07.14 23.2 1.3.0 In the Architecture chapter, corrected a text label in the Block Diagram of Intel Agilex 7 M-Series HBM2E Implementation figure in the Intel Agilex 7 M-Series UIB Architecture topic.
2023.06.26 23.2 1.3.0
  • In the Creating and Parameterizing chapter, modified the description of the AXI4-Lite support parameter in Table 10.
  • In the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface chapter:
    • In the Platform Designer-Only Interface topic, removed a note and modified the description of HBM2E pseudo-channel target NoC naming.
    • Added content to the User Access to the HBM2E Controller topic.
  • Added a new System Performance topic to the Performance chapter.
2023.04.21 23.1 1.2.0 Initial release.