High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 7/14/2023

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2.4. Intel Agilex® 7 M-Series HBM2E Controller Features

Intel Agilex® 7 FPGAs offer the following controller features.
  • User applications communicate with the HBMC via the hard memory NoC using the AXI4 Protocol.
  • There is one AXI4 interface per HBM2E pseudo-channel. Each HBM2E interface supports a maximum of sixteen AXI4 interfaces corresponding to the sixteen Pseudo Channels.
  • There are sixteen HBM controller cores, one for each pseudo-channel.
  • Each AXI interface supports a 256-bit Write Data interface and a 256-bit Read Data interface.
  • Each AXI interface connects to a target on the hard memory NoC.
  • The controller offers 32B and 64B access granularity, supporting HBM2E transactions with a burst length of 4 (BL4) and transactions composed of two successive BL4 transactions, referred to as pseudo-BL8 (pBL8).
  • The controller offers out-of-order command scheduling.
  • The controller refresh policy allows the controller to decide when to issue refresh requests.
  • The controller supports access to the HBM2E channel status registers, through the AXI4-Lite interface.
  • The controller supports data mask or error correction code (ECC). When you do not use data mask or ECC, you may use those bits as additional data bits.
  • The controller supports auto-precharge and temperature-based throttling.