High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 7/14/2023
Public

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3.5. Intel Agilex® 7 M-Series HBM2E Controller Architecture

The hardened HBM2E controller provides a total of sixteen controller cores, one per Pseudo Channel.

Each controller consists of a write and read data path and the control logic that helps to translate user commands to the HBM2E memory. The HBM2E controller logic accounts for the HBM2E memory specification timing and schedules commands in an efficient manner. The following figure shows a block diagram of the HBM2E controller, corresponding to channel 0. You can find more information about the interface timing details in the User AXI Interface Timing section.

Figure 6.  Intel Agilex® 7 M-Series HBM2E Controller Block Diagram