High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide

ID 773264
Date 7/14/2023

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6.1.3. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Latency

Read latency measures the number of clock cycles from the time the HBM2E controller receives a valid read address command, to the time that valid read data is available at the user interface. (In other words, from the instant the master asserts the ARVALID signal and the slave asserts the ARREADY signal, until the slave asserts the RVALID signal and the master asserts the RREADY signal.)

Read latency includes the controller command path latency to issue the read command to the HBM2E memory, memory read latency, and the delay in the read data path through the HBM2E memory controller. Command and data transfer via the hard memory NoC incur additional latency that is dependent on the relative position of NoC initiator and target. The effects of hard memory NoC latency are not reflected in simulation because they are placement-dependent.