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1. About the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
2. Introduction to High Bandwidth Memory
3. Intel Agilex® 7 M-Series HBM2E Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP
5. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Interface
6. High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Performance
7. Document Revision History for High Bandwidth Memory (HBM2E) Interface Intel FPGA IP User Guide
A. High Bandwidth Memory (HBM2E) Interface Intel® FPGA IP Intel® Quartus® Prime Software Flow
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5.5.3. ECC Error Counters Register
This per-pseudo-channel register counts the number of single-bit errors and double-bit errors detected by the HBM controller.
These counts can be used by software to track the reliability of the memory device. To read the ECC error counters register, issue a read command to the offset 32’h0560 for pseudo-channel 0 and 32’h0860 for pseudo-channel 1.
Bits | Access | Default | Name | Description |
---|---|---|---|---|
14:0 | RW1C | 15’h0 | SBE_ERRCNT | Number of correctable single-bit errors in pseudo-channel read responses detected by the HBM controller, since power up or counter reset. This counter saturates at maximum count. Any error after maximum count sets the overflow bit. |
15 | RW1C | 1’b0 | Reserved | Reserved. |
30:16 | RW1C | 15’h0 | DBE_ERRCNT | Number of uncorrectable (double-bit) errors in pseudo-channel read responses detected by the HBM controller, since power up or counter reset. This counter saturates at maximum count. Any error after maximum count sets the overflow bit. |
31 | RW1C | 1’b0 | Reserved | Reserved. |
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