FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 3/29/2024
Document Table of Contents

6.4. Top Level

After the Quartus® Prime project has finished executing, the design should look similar to the following image in the Quartus® Prime Project Navigator:
Figure 10. SoC Design Example Hierarchy
The top-level Verilog file and HPS configuration is derived directly from the GSRD designs located at RocketBoards.org:

The GSRD designs have been modified to include the FPGA AI Suite IP. All unnecessary logic has been removed, which provides a concise design example.

The main FPGA AI Suite SoC design example is contained within a single Platform Designer system, called system. Double-click this node in the Quartus® Prime Project Navigator to launch Platform Designer.