FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 3/29/2024
Document Table of Contents

6.5.1. The dla_0 Platform Designer Layer (dla.qsys)

The dla_0 layer contains the FPGA AI Suite IP and the Nios® V subsystem to provide streaming capabilities.

When incorporating the FPGA AI Suite IP into a custom design, you can use the dla.qsys file as a starting point for the new design.