FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 3/29/2024
Document Table of Contents

6.3.2. Nios® V Subsystem

Three IP modules make up the Nios® V subsystem:

  • mSGDMA (Avalon streaming to memory-mapped mode). This module is used to take the formatted input data stream and place it into system memory to create the FPGA AI Suite IP input buffers.
  • Mailbox (On-Chip Memory II Intel FPGA IP). This module is used to provide a communication API between the host-application and the Nios Subsystem. FPGA AI Suite IP command and status message are conveyed through this interface.
  • Nios® V processor. This module manages the FPGA AI Suite IP job-queue, mailbox and mSGDMA buffer allocation. Using the Nios® V processor offloads the latency-sensitive ingest and buffer management from the HPS.

All C source-code to the Nios® V application is provided. You can modify the Nios® software to enable third-party DMA controllers, if required.