FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 3/29/2024
Document Table of Contents

5.1. Building the Quartus® Prime Project

This design example includes prepackaged bitstreams but you can also use the build script provided to build bitstreams with custom architectures or recreate the original bitstreams, subject to IP license limitations.

The Quartus® Prime project consists of the FPGA AI Suite IP as well as IP to interface with the HPS and, in the case of the S2M variant, additional flow control IP.

FPGA AI Suite SoC Design Example Quick Start Tutorial shows how to use a specific architecture configuration file for the FPGA AI Suite IP, but you can use any other device-appropriate configuration file instead.