FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 3/29/2024
Document Table of Contents

6. FPGA AI Suite SoC Design Example Quartus® Prime System Architecture

The FPGA AI Suite SoC design examples provide two variants for demonstrating the FPGA AI Suite operation.

All designs are Platform Designer based systems.

There is a single top-level Verilog RTL file for instantiating the Platform Designer system.

These two variants demonstrate FPGA AI Suite operations in the two most common usage scenarios. These scenarios are as follows:

  • Memory to Memory (M2M): In this variant, the following steps occur:
    1. The Arm* processor host presents input data buffers to the FPGA AI Suite that are stored in a system memory.
    2. The FPGA AI Suite IP performs an inference on these buffers.
    3. The host system collects the inference results.
    This variant demonstrates the simplest use-case of the FPGA AI Suite.
  • Streaming to Memory (S2M): This variant offers a superset of the M2M functionality. The S2M variant demonstrates sending streaming input source data into the FPGA AI Suite IP and then collecting the results. An Avalon® streaming input captures live input data, stores the data into system memory, and then automatically triggers FPGA AI Suite IP inference operations.

    You can use this variant as a starting point for larger designs that stream input data to the FPGA AI Suite IP with minimal host intervention.