FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 3/29/2024
Document Table of Contents

6.5. The SoC Design Example Platform Designer System

At the center of the SoC design example is the Platform Designer system.

In Platform Designer, the SoC design example is separated into three hierarchical layers, the:

  • emif_0 : This layer contains the FPGA DDR4 External Memory Interface
  • dla_0 : This layer contains all the DLA IP and infrastructure IP
  • hps_0 : This layer contains all the ARM-HPS, ARM-EMIF and infrastructure IP for the ARM

The division of hierarchy demonstrates the sections of the design that are relevant to the solution. For example, if you want to target another board with a different external memory interface, you need to edit only the emif_0 layer.