FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 3/29/2024
Document Table of Contents

2. About the SoC Design Example

The FPGA AI Suite SoC design example shows how the Intel® Distribution of OpenVINO™ toolkit and the FPGA AI Suite support the CPU-offload deep learning acceleration model in an embedded system

The SoC design examples are implemented with the following components:

  • FPGA AI Suite IP
  • Intel® Distribution of OpenVINO™ toolkit
  • The community-supported OpenVINO™ ARM plugin
  • Sample hardware and software systems that illustrate the use of these components
  • Arm*-Linux build scripts for the Arria® 10 SX SoC and Agilex™ 7 I-Series SoC FPGA hard processor system (HPS) built using Yocto frameworks

For an easier initial experience, these design examples include prebuilt FPGA bitstreams and a Linux-compiled system image that correspond to pre-optimized FPGA AI Suite architecture files.

You can copy this disk-image to an SD card and insert the card into a supported FPGA development kit. Additionally, you can use the design example scripts to choose from a variety of architecture files and build (or rebuild) your own bitstreams, subject to IP licensing limitations.

SoC Design Example Execution Models

The SoC design example has two execution models:
  • Memory-to-memory (M2M) execution model, which provides a dla_benchmark interface to the inference engine, similar to the PCIe-based design examples.

    For design details, refer to Memory-to-Memory (M2M) Variant Design.

  • Streaming-to-memory (S2M) execution model that demonstrates a streaming data source

    For simplicity in this design example, the streaming data source is the SoC ARM CPU itself, which streams to a layout transform on the FPGA, but this design illustrates one of the suggested system architectures for any streaming source.

    For design details, refer to Streaming-to-Memory (S2M) Variant Design.

The design example is typically compiled for the S2M execution model, which supports both the M2M and S2M modes. A reduced functionality bitstream is also included as a compilation option, which supports only the M2M execution model.

The SoC design example has been optimized for simplicity, to create a flexible foundation that you can use to build more complex SoC designs.