FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 3/29/2024
Document Table of Contents

6.7. PLL Configuration

The FPGA AI Suite IP is designed to operate at high fMAX rates in Intel® FPGA devices. The SoC design example provides an IOPLL that provides the IP with a fast clock.

In the design example the external board 100 MHz reference clock is fed into the PLL and a 200 MHz output clock is produced. This clock feeds the FPGA AI Suite IP directly.

You can remove or alter this PLL if you want to profile different performance curves of the system.

The FPGA AI Suite dla_benchmark application has no runtime method to dynamically determine the PLL operating frequency in the SOC design. The frequency of 200 MHz has been set as a constant in this application source code. If you alter the PLL frequency, you must also alter the dla_benchmark application to match the new clock frequency. This matching ensures that the benchmark metrics accurately reflect the performance.

See dla_mmd_get_coredla_clock_freq in $COREDLA_WORK/runtime/coredla_device/mmd/hps_platform/acl_hps.cpp and change the return value accordingly.