MACsec Intel FPGA System Design User Guide

ID 767516
Date 3/03/2023

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Document Table of Contents E/F-Tile Hard IP Reset Sequence

Figure 12. Waveform of the Hard IP Reset Sequence
From the figure above, we see that there are several steps for IP reset.
  1. The i_csr_rst_n reset returns all Ethernet registers to their original values, including the statistics counters.
  2. The assertion of i_tx_pll_locked leads to desertion of the i_csr_rst_n output signal.
  3. Once i_csr_rst_n deserted, its leads to assertion of o_tx_lane_stable output signal.
  4. After deassertion of i_csr_rst_n reset and once PHY is ready to receive data it asserts o_rx_block_lock and io_rx_pcs_ready output signal.
  5. Asserting the i_csr_rst_n reset leads to desertion of i_tx_lane_stable, o_rx_block_lock and rx_pcs_ready output signal.