MACsec Intel FPGA System Design User Guide

ID 767516
Date 3/03/2023

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Document Table of Contents

4. Parameters

This table below lists the parameters.
Table 8.  
Name Default Value Description
PCIE_LANE_W 16 Number of PCIe lanes; x16 or x8.
NUM_MACSEC_INST 2 Number of MACsec blocks in the design.
MACSEC_CSR_ADDR_W 25 32MB CSR address space by default.
MACSEC_CSR_DATA_W 64 64 bit CSR data path with unaligned 32 bit support too.
PKTCLI_CSR_ADDR_W 12 4K CSR address space for packet client.
PKTCLI_CSR_DATA_W 32 32 bit CSR data path for packet client.
NUM_MAC_CHANNELS 2 Matches with NUM_MACSEC_INST as MAC works with MACsec.
NUM_LANES 1 Number of QSFP lanes. For 25G its 1; for 100G its 4.
TILE_DATA_WIDTH 64 MAC AVST data width. For 25G it is 64; for 100G it is 512.
TILE_EMPTY_WIDTH 3 MAC AVST empty width. For 25G it is 3; for 100G it is 6.