F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 4/03/2024
Document Table of Contents XON/XOFF Pause Frames

Priority-based Flow Control

You can trigger the 50G Ethernet Intel FPGA IP to transmit PFC XOFF frame with a pause duration that is specified in TX Flow Control Quanta register by updating the pause_insert_tx0 and pause_insert_tx1 input signals or TX flow control registers. If an enabled priority queue is in the XOFF condition, a new PFC frame is transmitted after the minimum time gap. You specify the minimum time gap in the per priority queue TX Flow Control Signal XOFF Request Hold Quanta register. The minimum time gap between two consecutive PFC frames is 1 pause quanta or 512-bit times. PFC frame transmission ends when none of the PFC interfaces of all enabled priority queues is requesting PFC frames.

A transition from XOFF to XON in any enabled priority queue triggers the IP to transmit a PFC frame with pause quanta of 0 for the associated priority queue. The IP sends a single XON flow control frame. In the rare case that the XON frame is lost or corrupted, the remote partner should still be able to resume transmission. The remote partner resumes transmission after the duration or the pause quanta value specified in the previous XOFF flow control frame expires.

Standard Flow Control

In the case of standard flow control, the IP transmits Pause frames instead of PFC frames. The transmission behavior is identical.

When the IP is in standard flow control mode and receives a Pause frame, the IP stops processing TX client data, either immediately or at the next frame boundary. Client data transmission resumes when all of the following conditions are true:

  • The time specified by the pause quanta has elapsed and there is no new quanta value.
  • A valid pause frame with 0 pause duration has been received.

A Pause frame has no effect if the associated TX Flow Control Enable register bit is set to disable XON and XOFF flow control.