F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 4/03/2024
Document Table of Contents

8.1. TX MAC Registers

Table 21.  TX MAC Registers
Addr Name Description Reset Access

TX MAC revision ID for 50G TX MAC CSRs.

0x2007 2022

0x401 TXMAC_SCRATCH Scratch register available for testing. 0x0000 0000 RW
0x402 TXMAC_NAME_0

First 4 characters of IP core variation identifier string, "50gMACTxCSR".

0x3235 674D


0x403 TXMAC_NAME_1

Next 4 characters of IP core variation identifier string, "ACTx".

0x4143 5478


0x404 TXMAC_NAME_2 Final 4 characters of IP core variation identifier string, "0CSR". The "0" is unprintable. 0x0043 5352



Link Fault Configuration Register. The following bits are defined:

  • Force Remote Fault bit[3]: When link fault generation is enabled, stops data transmission and forces transmission of a remote fault.
  • Disable Remote Fault bit[2]: When both link fault reporting and unidirectional transport are enabled, the core transmits data and does not transmit remote faults (RF). This bit takes effect when the value of this register is 28'hX4'b0111.
  • Unidir Enable bit[1]: When asserted, the core includes Clause 66 support for the remote link fault reporting on the Ethernet link.
  • Link Fault Reporting Enable bit[0]: The following encodings are defined:
    • 1'b1: The PCS generates the proper fault sequence on Ethernet link, when conditions are met.
    • 1'b0: The PCS does not generate the fault sequence.
28'hX_4'b0001 2


0x407 MAX_TX_SIZE_CONFIG Specifies the maximum TX frame length. Frames that are longer are considered oversized. They are transmitted, but also increment the CNTR_TX_OVERSIZE register.

Bits [31:16] of this register are Reserved.

0xXXXX 2580 2


0x40A TXMAC_CONTROL TX MAC Control Register. A single bit is defined:
  • Bit[1]: VLAN detection disabled. This bit is deasserted by default, implying VLAN detection is enabled.
30'hX2'b0X 2 RW
2 X means "Don't Care".