F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 4/03/2024
Document Table of Contents

5.1.1. F-Tile Low Latency 50G Ethernet Intel® FPGA IP TX MAC Datapath

The TX MAC module receives the client payload data with the destination and source addresses. It then adds, appends, or updates various header fields in accordance with the configuration specified. The MAC does not modify the destination address, the source address, or the payload received from the client. However, the TX MAC module adds a preamble, if the IP is not configured to receive the preamble from user logic. It pads the payload of frames greater than eight bytes to satisfy the minimum Ethernet frame payload of 46 bytes. By default, the MAC inserts the CRC bytes. The TX MAC module inserts IDLE bytes to maintain an average IPG of 12.

Figure 8. Typical Client Frame at the Transmit InterfaceIllustrates the changes that the TX MAC makes to the client frame. This figure uses the following notational conventions:
  • <p> = payload size, which is arbitrarily large
  • <s> = number of padding bytes (0–46)
  • <g> = number of IPG bytes
Figure 9. TX MAC Functions