F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 4/03/2024
Document Table of Contents

3.5.1. Pin Assignments

When you integrate your 50G Ethernet Intel FPGA IP instance in your design, you must make appropriate pin assignments. While compiling the IP alone, you can create virtual pins to avoid making specific pin assignments for top-level signals. When you are ready to map the design to hardware, you can change to the correct pin assignments.