MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/02/2023
Public

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5.2. Packet Parser and Classifier

The MACsec Packet Parser and Classifier is responsible for parsing and classifying the incoming packets. The header extracted from the packets is used in subsequent blocks for processing. The incoming packets are parsed and classified based on the packet content dependent on whether it is an encryption or decryption lane.

The table below shows an Ethernet packet type that enters a Packet Parser/Classifier block through a Transmit Tx lane Controlled port. The packet parser extracts all the fields listed in the table below from the packet and the packet classifier classifies the result of parsing. The extracted fields are then sent together with the packet for subsequent stage processing.
Table 37.  Fields Extracted by Packet Parser
Field Size (Bytes)
DMAC 6
SMAC 6
VLAN tag 4
Stack VLAN tag 4
Ethertype/Length 2
Payload 44-9578
The table below shows an Ethernet packet type that enters Packet Parser/Classifier block through a Decryption Rx lane Common port. The packet parser extracts all the fields listed in the table below from the packet and the packet classifier classifies the result of the parsing. The extracted fields are then sent together with the packet for subsequent stage processing.
Table 38.  Ethernet Packet Type Entering Packet Parser/Classifier Block
  Field Size (Bytes)
- DMAC 6
SMAC 6
802.1Q (VLAN tag; optional) 4
802.1 AE Header MACsec Ethertype (0x88E5) 2
TCI/AN 1
SL 1
Packet Number 4
SCI (optional) 8
- 802.1Q 4
Ethertype/Length 2
Payload 44-9546
ICV 16