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1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Functional Description
6. Configuration Registers for MACsec IP
7. MACsec Intel® FPGA IP Example Design
8. MACsec Intel FPGA IP User Guide Archives
9. Document Revision History for the MACsec Intel FPGA IP User Guide
2.2.1.1. Common Port Mux Interface
2.2.1.2. Common Port Demux Interface
2.2.1.3. Controlled Port Mux Interface
2.2.1.4. Controlled Port Demux Interface
2.2.1.5. Uncontrolled Port RX Interface
2.2.1.6. Uncontrolled Port TX Interface
2.2.1.7. Management Interface
2.2.1.8. Decrypt Port Mux Management Interface
2.2.1.9. Decrypt Port Demux Management Interface
2.2.1.10. Encrypt Port Mux Management Interface
2.2.1.11. Encrypt Port Demux Management Interface
2.2.1.12. Crypto IP Management Bus
2.2.1.13. Miscellaneous Control Signals
2.2.2.1. Common Port Mux Interface Waveform
2.2.2.2. Common Port Demux Interface Waveform
2.2.2.3. Controlled Port Mux Interface Waveform
2.2.2.4. Controlled Port Demux Interface Waveform
2.2.2.5. Uncontrolled Port RX Interface Waveform
2.2.2.6. Uncontrolled Port TX Interface Waveform
2.2.2.7. Crypto RX Waveform
2.2.2.8. Crypto TX Waveform
2.2.2.9. MACsec Management Interface (Read)
2.2.2.10. MACsec Management Interface (Write)
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5.4.3.2. VLAN Tag (Not in Clear)
The following diagram shows the packet format when it is a VLAN tag. The VLAN tag is encrypted together with the payload. This mode can be enabled through setting the PORTX_VLAN_CLEAR parameter to DISABLE. All the port-specific VLAN_CLEAR settings must be set to the same value. This example is showing a single VLAN packet format. In the case of a double VLAN tag detected in the packet, for example, SVLAN - CVLAN, only the outer VLAN tag (SVLAN) is put in cleartext. For a single VLAN tag, for example, CVLAN, the CVLAN tag is put in cleartext.
Field (TData) | DMAC | SMAC | 802.1Q | Ethertype | Payload (plaintext) |
---|---|---|---|---|---|
Size (Bytes) | 6 | 6 | 4 | 2 | 46 - 9582 |
Figure 27. VLAN Tag (Not in Clear)