MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/02/2023
Public

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5.7.2. Byte Order Swapping

The Crypto QHIP has little endian byte order. This means that for the key, IV and data, bits [7:0] contain the first byte of the corresponding string.

Below is an example of the Key and data byte order based on IEEE 802.1AE specification:
  1. For SCI, PN, IV and key, the register address order is illustrated previously. The leftmost byte is the MSB byte.
  2. Byte swapping is done in the MACsec IP for these CSRs before it is sent to the Crypto QHIP.
Table 51.  Example of Key and Data Byte Order for Crypto QHIP
DA 84C5D513D2AA
SA F6E5BBD27277
Ethertype 88E5
SCI[63:0] 0x7CFDE9F9E33724C6
PN[63:0] 0x000000008932D612
IV: 7CFDE9F9E33724C68932D612

Key[63:0]

Key[127:64]

Key[191:128]

Key[255:192]

0000000000000000

0000000000000000

866D0CBBC55A7A90

013FE00B5F11BE7F

Plaintext

08000F101112131415161718191A1B1C 1D1E1F202122232425262728292A2B2C 2D2E2F303132333435363738393A3B00

06

AAD 84C5D513D2AAF6E5BBD2727788E52F00 8932D6127CFDE9F9E33724C6

Within 16B segment, IV is swapped before it is sent to the Crypto:

tdata[127:0] = 0x12D63289C62437E3F9E9FD7C

128b key is swapped before it is sent to the Crypto:

tdata[255:128] = 0x00000000000000000000000000000000

tdata[127:0] = 0x907A5AC5BB0C6D867FBE115F0BE03F01