|Intel® Quartus® Prime Design Suite 23.3
|IP Version 2.1.0
The MACsec Intel® FPGA IP is provided for evaluation purposes. Features may differ substantially or be dropped in final production. All product plans are subject to change without notice. Statements in this document that refer to future plans or expectations are forward-looking statements. These statements are based on current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in such statements. For more information on the factors that could cause actual results to differ materially, see our most recent earnings release and SEC filings at http://www.intc.com.