MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

2.2.1.8. Decrypt Port Mux Management Interface

Note: This interface is used to switch the Decrypt Port Mux from "Store and Forward" mode to "Cut Through" mode.
Table 14.  Decrypt Port Mux Management Interface
Signal Name Width Direction Description
rx_mux_app_pp_lite_awaddr 25 Input Write address
rx_mux_app_pp_lite_awvalid 1 Input Write address valid
rx_mux_app_pp_lite_wdata 32 Input Write data
rx_mux_app_pp_lite_wstrb 4 Input Indicates the byte lanes that hold valid data
rx_mux_app_pp_lite_wvalid 1 Input Write data valid
rx_mux_app_pp_lite_bready 1 Input Indicates that the master can accept a write response
rx_mux_app_pp_lite_araddr 25 Input Read address
rx_mux_app_pp_lite_arvalid 1 Input Read address channel valid
rx_mux_app_pp_lite_rready 1 Input Indicates that the master can accept the read data and response
rx_mux_pp_app_lite_awready 1 Output Indicates slave is ready to accept a write transaction
rx_mux_pp_app_lite_wready 1 Output Indicates that the salve can accept the write data
rx_mux_pp_app_lite_bresp 2 Output Indicates the status of the write transaction
rx_mux_pp_app_lite_bvalid 1 Output Write response valid
rx_mux_pp_app_lite_arready 1 Output Indicates that the slave is ready to accept an read address transaction
rx_mux_pp_app_lite_rdata 32 Output Read data
rx_mux_pp_app_lite_rvalid 1 Output Read data valid
rx_mux_pp_app_lite_rresp 2 Output Indicates the status of the read transfer
rx_mux_pp_app_rst_rdy 1 Output When 1'b1, indicates that the mux has completed its reset sequence, is currently out of reset, and is ready for a new reset sequence.
rx_mux_pp_app_cold_rst_ack_n 1 Output Acknowledge signal for mux's internal subsystem_cold_rst_n. Active low.
rx_mux_pp_app_warm_rst_ack_n 1 Output Acknowledge signal for mux's internal subsystem_warm_rst_n. Active low.