MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/02/2023
Public

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5.4.1. Channel Allocation

When starting a new flow/channel in the Crypto AES, you need to send the key and channel ID 1 cycle before sending the payload. The table below shows 2 cycles of the channel allocation on channel 0 and 1 (TID).
Table 43.  Two Cycles of Channel Allocation on Channels 0 and 1
Interface Event
AXI-ST TID 0 1
AXI-ST TKEEP 00000000_00000000_00000000_00000000 11111111_11111111_11111111_11111111 00000000_00000000_00000000_00000000 00000000_00000000_11111111_11111111
AXI-ST TUSER Channel Key Allocation Channel Key Allocation
algorithm_types 0 0
encrypt_decrypt 0 0
key_128b_256b 1 0
modes[5:0] 100010 100010
AXI-ST TDATA    
[511:384]    
[383:256]    
[255:128] KEY1[255:128]  
[127:0] KEY1[127:0] KEY2[127:0]