MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/02/2023
Public

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2.2.1.7. Management Interface

Table 13.  Management Interface
Signal Name Width Direction Description
app_ip_lite_clk 1 Input Clock
app_ip_lite_areset_n 1 Input Asynchronous reset
Write Address Channel
app_ip_lite_awaddr 25 Input Write address
app_ip_lite_awprot 3 Input Privilege and security level of the transaction
app_ip_lite_awvalid 1 Input Write address valid
ip_app_lite_awready 1 Output Indicates slave is ready to accept a write transaction
Write Data Channel
app_ip_lite_wdata 64 Input Write data
app_ip_lite_wstrb 8 Input Indicates the byte lanes that hold valid data
app_ip_lite_wvalid 1 Input Write data valid
ip_app_lite_wready 1 Output Indicates that the slave can accept the write data
Write Response Channel
ip_app_lite_bresp 2 Output Indicates the status of the write transaction
ip_app_lite_bvalid 1 Output Write response valid
app_ip_lite_bready 1 Input Indicates that the master can accept a write response
Read Address Channel
app_ip_lite_araddr 25 Input Read address
app_ip_lite_arprot 3 Input Read address channel privilege and security attribute
app_ip_lite_arvalid 1 Input Read address channel valid
ip_app_lite_arready 1 Output Indicates that the slave is ready to accept an read address transaction
Read Data Channel
ip_app_lite_rdata 64 Output Read data
ip_app_lite_rvalid 1 Output Read data valid
app_ip_lite_rready 1 Input Indicates that the master can accept the read data and response
ip_app_lite_rresp 2 Output Indicates the status of the read transfer