MACsec Intel® FPGA IP User Guide

ID 736108
Date 10/02/2023

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5.1.4. AXI-ST Ready Latency

Figure 22. AXI-ST Ready Latency

The MACsec IP implements a configurable AXI-ST ready latency. The supported range of ready latency is 0-16. All the AXI-ST responders for AES and IP user interfaces implement this ready latency and it can be configured in the IP GUI.