Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 12/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Installation and Setup 3. Getting Started with RiscFree* IDE 4. Debug Setup for Nios® V Processor System 5. Debug Setup for Arm* Hard Processor System 6. Debugging with RiscFree* IDE 7. Debugging with Command-Line Interface 8. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 9. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Intel® Quartus® Prime Software Support 1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2. Installation and Setup x
2.1. Bundled Installation with the Intel® Quartus® Prime Software 2.2. Standalone Installation
2.2. Standalone Installation x
2.2.1. Standalone Installation with Supported Intel® Quartus® Prime Software 2.2.2. Standalone Installation with the Intel® Quartus® Prime Programmer and Tools
3. Getting Started with RiscFree* IDE x
3.1. Graphical User Interface 3.2. Command Line Interface 3.3. Ashling* RiscFree* IDE for Intel® FPGAs Interaction with Intel® Simics® Simulator for Intel® FPGAs
4. Debug Setup for Nios® V Processor System x
4.1. Importing Nios® V Processor Project 4.2. Building Nios® V Processor Project 4.3. Setting Debug Configurations and Downloading Nios® V Processor Project Using RiscFree* IDE
5. Debug Setup for Arm* Hard Processor System x
5.1. Pre-requisite for Debugging Arm* HPS Project 5.2. Importing Arm* HPS Project 5.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
6. Debugging with RiscFree* IDE x
6.1. Debug Features in RiscFree* IDE 6.2. Processor System Debug 6.3. Heterogeneous Multicore Debug 6.4. Debugging µC/OS-II Application 6.5. Debugging FreeRTOS Application 6.6. Debugging Zephyr Application 6.7. Arm* HPS On-Chip Trace 6.8. Debugging the Arm* Linux Kernel 6.9. Debugging Target Software in an Intel® Simics Simulator Session
6.1. Debug Features in RiscFree* IDE x
6.1.1. Viewing Global Variables 6.1.2. Launching Memory Browser 6.1.3. Debugger Console 6.1.4. Specifying the SVD File 6.1.5. Breakpoint Settings 6.1.6. JTAG UART Output Terminal
6.2. Processor System Debug x
6.2.1. GUI for Debugging
6.3. Heterogeneous Multicore Debug x
6.3.1. Importing Nios® V Processor and Arm* HPS Projects 6.3.2. Setting Core Configuration
6.7. Arm* HPS On-Chip Trace x
6.7.1. Trace Bar 6.7.2. Trace View
6.8. Debugging the Arm* Linux Kernel x
6.8.1. Preparing Linux for Kernel Debugging 6.8.2. Debugging the Arm* HPS Linux Kernel
7. Debugging with Command-Line Interface x
7.1. Running Ashling* GBD Server 7.2. Running GDB 7.3. Nios® V Processor Example 7.4. ARM HPS Core Example
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Debugging with Command-Line Interface
8. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
9. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

7.1. Running Ashling* GBD Server

The Ashling* GDBServer connects to the processor core with a remote GDB, which allows you to debug the software applications remotely. The Ashling* GDBServer must be ready before running the GDB.
Table 14.   Ashling* GDBServer
Processor Core Executables File
Nios® V Processor <Intel Quartus Prime installation directory>/riscfree/debugger/gdbserver-riscv/ash-riscv-gdb-server.exe
Arm* HPS core <Intel Quartus Prime installation directory>/riscfree/debugger/gdbserver-arm/ash-arm-gdb-server.exe
By invoking the Ashling* GDBServer with --help, you can get more information from the executables’ internal documentation about the supported GDB MONITOR commands. The table below lists the common options for starting the Ashling* GDBServer.
Table 15.  Options and Description
Options Mandatory Description
--device <IDCODE> Yes

Specifies the IDCODE of the target device.

Use jtagconfig to display the device IDCODE.

--autodetect true Yes Enable JTAG scan chain auto-detection on the specified IDCODE.
--probe-type usb-blaster-2 Yes Select Intel® FPGA Download Cable II (USB-Blaster 2) as the debug probe.
--tap-number <number> No Select the TAP (test access port) with the specified IDCODE (when there is more than one TAP with the same IDCODE).
--core-number <number> No

Select the processor core within the same device.

  • Use jtagconfig to display the Nios® V processor core number.
  • Refer to the Hard Processor System Technical Reference Manual for the number of Arm* cores in the device.
--jtag-frequency <frequency> No
Specifies the JTAG frequency. The following are the valid inputs:
  • 1 MHz, 2 MHz, 3 MHz, 4 Mhz, 4.8 Mhz, 6 MHz, 16 MHz, 24 MHz
  • auto-adjust (to specify the same frequency as jtagserver)
--instance <number> No Select the probe based on the serial number.
--gdb-port <port> No

Specifies the TCP port to connect to GDB.

Default TCP at 2331.
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