Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

ID 730783
Date 12/14/2023

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5. Debug Setup for Arm* Hard Processor System

This section provides guidance on debugging Arm* HPS core using the RiscFree* IDE debugging tool and accessing the hardware modules (for example, peripherals) that are instantiated in the RiscFree* IDE FPGA design. This tutorial is based on the Intel® FPGA example design from Ashling.
Note: RiscFree* IDE supports Arm* HPS standalone debug.