Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

ID 730783
Date 12/14/2023
Document Table of Contents

6.1.5. Breakpoint Settings

RiscFree* IDE supports SoC-wide breakpoint and core-specific software breakpoints in shared code.

SoC-wide Breakpoint

A single breakpoint can halt all cores in active debug launches. To enable SoC-wide breakpoint, go to Run > Enable SoC Wide Breakpoint.

Core-specific Software Breakpoints

This breakpoint can only halt a specified core if debug is running for common code shared between multiple cores. To enable this feature, go to Window > Preferences > C/C++ > Debug > GDB and select Set breakpoint for active debug context only. This option is unchecked by default. If this is unchecked, any breakpoint set in shared code is applicable for all the cores sharing the code.