Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 12/14/2023
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Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Installation and Setup 3. Getting Started with RiscFree* IDE 4. Debug Setup for Nios® V Processor System 5. Debug Setup for Arm* Hard Processor System 6. Debugging with RiscFree* IDE 7. Debugging with Command-Line Interface 8. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 9. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Intel® Quartus® Prime Software Support 1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2. Installation and Setup x
2.1. Bundled Installation with the Intel® Quartus® Prime Software 2.2. Standalone Installation
2.2. Standalone Installation x
2.2.1. Standalone Installation with Supported Intel® Quartus® Prime Software 2.2.2. Standalone Installation with the Intel® Quartus® Prime Programmer and Tools
3. Getting Started with RiscFree* IDE x
3.1. Graphical User Interface 3.2. Command Line Interface 3.3. Ashling* RiscFree* IDE for Intel® FPGAs Interaction with Intel® Simics® Simulator for Intel® FPGAs
4. Debug Setup for Nios® V Processor System x
4.1. Importing Nios® V Processor Project 4.2. Building Nios® V Processor Project 4.3. Setting Debug Configurations and Downloading Nios® V Processor Project Using RiscFree* IDE
5. Debug Setup for Arm* Hard Processor System x
5.1. Pre-requisite for Debugging Arm* HPS Project 5.2. Importing Arm* HPS Project 5.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
6. Debugging with RiscFree* IDE x
6.1. Debug Features in RiscFree* IDE 6.2. Processor System Debug 6.3. Heterogeneous Multicore Debug 6.4. Debugging µC/OS-II Application 6.5. Debugging FreeRTOS Application 6.6. Debugging Zephyr Application 6.7. Arm* HPS On-Chip Trace 6.8. Debugging the Arm* Linux Kernel 6.9. Debugging Target Software in an Intel® Simics Simulator Session
6.1. Debug Features in RiscFree* IDE x
6.1.1. Viewing Global Variables 6.1.2. Launching Memory Browser 6.1.3. Debugger Console 6.1.4. Specifying the SVD File 6.1.5. Breakpoint Settings 6.1.6. JTAG UART Output Terminal
6.2. Processor System Debug x
6.2.1. GUI for Debugging
6.3. Heterogeneous Multicore Debug x
6.3.1. Importing Nios® V Processor and Arm* HPS Projects 6.3.2. Setting Core Configuration
6.7. Arm* HPS On-Chip Trace x
6.7.1. Trace Bar 6.7.2. Trace View
6.8. Debugging the Arm* Linux Kernel x
6.8.1. Preparing Linux for Kernel Debugging 6.8.2. Debugging the Arm* HPS Linux Kernel
7. Debugging with Command-Line Interface x
7.1. Running Ashling* GBD Server 7.2. Running GDB 7.3. Nios® V Processor Example 7.4. ARM HPS Core Example
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Debugging with Command-Line Interface
8. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
9. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

4. Debug Setup for Nios® V Processor System

You can develop software for the Nios® V processor effectively using Intel® FPGA development kit. The development kit includes documentation, a ready-made evaluation board, a getting-started reference design, and all the development tools necessary to write Nios® V processor programs.

Modifying existing code is a common, easy way to learn to start writing software in a new environment. The Nios® V Processor Intel® FPGA IP provides example software designs that you can examine, modify, and use in your own programs. The examples are documented in the Nios® V Embedded Processor Design Handbook and are ready to compile.

This section guides you through the fundamental operations in RiscFree* IDE for Nios® V processors, providing steps for the following applications:

  • Importing an application project for the Nios® V processor, with the board support package (BSP) project required to interface with your hardware.
  • Building an application and BSP projects in RiscFree* IDE.
  • Running the software on an Intel® FPGA development board.

The following operating systems support Nios® V processor applications:

  • Intel® HAL (Bare-Metal)
  • MicroC/OS-II (µC/OS-II)
  • Zephyr®
  • FreeRTOS™

Section Content
Importing Nios V Processor Project
Building Nios V Processor Project
Setting Debug Configurations and Downloading Nios V Processor Project Using RiscFree IDE

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