Nios® V Embedded Processor Design Handbook

ID 726952
Date 10/02/2023

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Document Table of Contents CPU Architecture

Table 10.  CPU Architecture Tab Parameters
CPU Architecture Description
Enable Pipelining in CPU
  • Enable this option to instantiate pipelined Nios® V/m processor.
    • IPC is higher at the cost of higher logic area and lower Fmax frequency.
  • Disable this option to instantiate non-pipelined Nios® V/m processor.
    • Has similar core performance with the Nios® V/c processor.
    • Supports debugging and interrupt capability
    • Lower logic area and higher Fmax frequency at the cost of lower IPC.
    • “A” Extension is disabled.
Enable Atomic Extension
  • Enable this option to add atomic operation (“A” Extension) in the processor core.