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1. About the Nios® V Embedded Processor
2. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Software and Platform Designer
3. Nios® V Processor Software System Design
4. Nios® V Processor Configuration and Booting Solutions
5. Nios® V Processor - Using the MicroC/TCP-IP Stack
6. Nios® V Processor Debugging, Verifying, and Simulating
7. Nios® V Processor — Remote System Update
8. Nios® V Processor — Using Custom Instruction
9. Nios® V Embedded Processor Design Handbook Archives
10. Document Revision History for the Nios® V Embedded Processor Design Handbook
4.1. Introduction
4.2. Linking Applications
4.3. Nios® V Processor Booting Methods
4.4. Introduction to Nios® V Processor Booting Methods
4.5. Nios® V Processor Booting from Configuration QSPI Flash
4.6. Nios® V Processor Booting from On-Chip Memory (OCRAM)
4.7. Nios® V Processor Booting from Tightly Coupled Memory (TCM)
4.8. Summary of Nios® V Processor Vector Configuration and BSP Settings
6.5.1. Prerequisites
6.5.2. Setting Up and Generating Your Simulation Environment in Platform Designer
6.5.3. Creating Nios V Processor Software
6.5.4. Generating Memory Initialization File
6.5.5. Generating System Simulation Files
6.5.6. Running Simulation in the QuestaSim Simulator Using Command Line
8.2.3. Acquiring the Example Design File
To generate the example design, perform the following steps:
- Go to Intel® FPGA Design Store.
- Search for Intel Agilex® 7 FPGA - Custom Instruction Design on Nios® V/g Processor.
- Click on the link at the title.
- Accept the Software License Agreement.
- Download the package according to the Intel® Quartus® Prime software version of your host PC.
- Refer to the readme.txt for the how-to guide.
File | Description |
---|---|
custom_logic/ | Contains the custom logic processing engines, which holds eight different operations. |
hw/ | Contains file necessary to run the hardware project. |
ready_to_test/ | Contains pre-built hardware and software binaries to run the design on the target hardware. For this package, the target hardware is Intel® Arria® 10 SoC development kit. This design is targeted on Intel Agilex® 7 F-Series FPGA Development Kit DK-DEV-AGF014EA. |
scripts/ | Consists of scripts to build the design. |
sw/ | Contains software application files. |
readme.txt | Contains description and steps to apply the pre-built binaries or rebuild the binaries from scratch. |
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