F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

ID 720998
Date 4/01/2024
Public
Document Table of Contents

1.1. IP Core Overview

The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP is the multirate version of F-Tile PMA/FEC Direct PHY Intel FPGA IP, which is meant for dynamic reconfiguration usage.
The IP provides the options to specify the startup settings, and targeted dynamic reconfiguration settings. During generation, the IP instantiates the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP for its startup and dynamic reconfiguration profiles.
Note: You can currently use the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP only along with the F-Tile Dynamic Reconfiguration Suite Intel FPGA IP. Refer to the F-Tile Dynamic Reconfiguration Design Example User Guide for quick reference on how to connect and simulate these two IPs.

The IP currently supports the following reconfiguration modes:
  • Data rate reconfiguration
  • Reference clock switching
  • PMA width reconfiguration
  • RS-FEC mode reconfiguration
  • Duplex and simplex mode reconfiguration
  • PMA Direct to FEC Direct mode reconfiguration
  • FEC to non-FEC mode reconfiguration
  • PAM4 to NRZ signaling reconfiguration
  • TX FGT PLL reconfiguration
  • RX FGT CDR reconfiguration
  • TX/RX user clock reconfiguration
The IP currently does not support the following reconfiguration modes:
  • FGT to FHT reconfiguration
  • Duplex mode to simplex mode reconfiguration
  • System PLL reconfiguration
  • Reference clock reconfiguration for system PLL

The F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP allows you to enable the Datapath Avalon® Memory-Mapped Interface to access the soft CSR and reconfiguration soft CSR registers and PMA Avalon® Memory-Mapped Interface to access the PMA registers.