F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

Download PDF
ID 720998
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers Overview 7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives 8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Related Documentation
1.1. IP Core Overview x
1.1.1. Reconfiguration Group 1.1.2. Base Profile 1.1.3. Secondary Profiles 1.1.4. Startup Profile 1.1.5. Supported Reconfiguration Groups
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX and RX Parallel and Serial Signals 2.4. Custom Cadence Control and Status Signals 2.5. TX and RX PMA Status Signals 2.6. RS-FEC Signals 2.7. TX and RX PMA FIFO Signals 2.8. PMA Avalon Memory-Mapped Signals 2.9. Datapath Avalon Memory-Mapped Signals
3. Parameters x
3.1. Dynamic Reconfiguration QSF Settings 3.2. QSF settings for Different Reconfiguration Profiles 3.3. Generating IP-XACT File
3.2. QSF settings for Different Reconfiguration Profiles x
3.2.1. Bypass RX Adaptation QSF Settings
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
4.4. Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core x
4.4.1. Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core
6. Configuration Registers Overview x
6.1. Controlling the Reconfiguration Soft CSR Registers for Dynamic Reconfiguration 6.2. Configuration Registers
6.2. Configuration Registers x
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers 6.2.2. F-Tile PMA/FEC Direct PHY Multirate Intel® FPGA IP Core Soft CSR Registers
6.2.1. F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers x
6.2.1.1. Controlling the Reconfiguration Soft CSR with Fractures
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers Overview
7. F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide Archives
8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

8. Document Revision History for the F-Tile PMA and FEC Direct PHY Multirate Intel® FPGA IP User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.04.01 24.1 4.1.0 Made the following changes:
  • Added Agilex™ 9 device information in the Device Family Support section.
  • Updated the Select FHT Lane PLL refclk source parameter settings in the Parameter Settings: TX FHT Datapath Options PN (N=0-32) table.
2023.12.04 23.4 4.0.0 Made the following changes:
  • Updated information about FHT reconfiguration support in IP Core Overview, Interface Overview, and Parameters sections.
  • Added information about setting the TX FHT PMA PN (N=0-32) and RX FHT PMA PN (N=0-32) parameters in the Parameters section.
  • Added information about setting the Analog Parameters using the IP parameter editor in the Parameters section.
2023.04.03 23.1 2.0.3
  • Added a note about "In the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP, the core FIFO interface always uses double width data transfer" under table 9 in TX and RX Parallel and Serial Signals.
  • Removed the following two parameters in the IP Parameter Editor: General Tab and updated the screenshot.
    • Reconfiguration clock source
    • Selected coreclkin clock network
  • Removed set_instance_assignment -name IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL -to <bb_instance_hpath> <clock-port-name> QSF Settings and its description in the Dynamic Reconfiguration QSF Settings.
  • Added new topic: Generating IP-XACT File.
  • Changed the byte address 16’h800 - 16’h818 to 20'h800 - 20'h818 in F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers.
  • Updated reconfiguration Soft CSR byte address screenshot from 16'h820-82C to 20'h820-82C in Controlling the Reconfiguration Soft CSR with Fractures.
  • Updated 16'h820 - 828 to 20'h820 - 828 in F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core Soft CSR Registers.
  • Added a foot note to the following table:
    • F-Tile PMA/FEC Direct PHY Intel FPGA IP Soft CSR Registers table in the F-Tile PMA/FEC Direct PHY Intel FPGA IP Core Soft CSR Registers.
    • F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core Soft CSR Registers in the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core Soft CSR Registers.
  • Updated product family name to "Intel Agilex 7."
2022.12.19 22.4 2.0.2 Made the following changes:
  • Updated description for the Reconfiguration clock source parameter in Parameter Settings: General Tab table.
  • Added .qsf setting and description for IP_RECONFIG_GROUP_MASTER_CLOCK_CHANNEL in Dynamic Reconfiguration QSF Setting for the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP table.
2022.09.26 22.3 2.0.1 Made the following changes:
  • Deleted note in IP Core Overview that hardware support is planned for a future release.
  • Updated Reconfiguration clock source supported values range in Parameter Settings: General Tab table.
  • Updated Number of secondary profiles supported values to start from one in Parameter Settings: General Tab table.
  • Added new sections Dynamic Reconfiguration QSF settings, QSF settings for Different Reconfiguration Profiles, and Bypass RX Adaptation QSF Settings about .qsf assignment settings.
  • Added step 6. about adding .qsf assignment settings in Steps to Configure the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core section.
2022.06.21 22.2 2.0.0 Made the following changes:
  • Updated several parameter names and figures based on the updated IP GUI.
  • Updated the Available Reconfiguration Groups for FGT PMA table in Supported Reconfiguration Groups.
  • Removed tx_coreclkin and rx_coreclkin signals and replaced with coreclkin in Clock signals.
  • Updated the custom cadence signal names in Custom Cadence Control and Status Signals table.
  • Updated Reconfiguration group supported values in Parameter Settings: General Tab table.
  • Updated Number of secondary profiles supported values in Parameter Settings: General Tab table.
  • Added new parameters Reconfiguration clock source and Selected coreclkin clock network parameters to the Parameter Settings: General Tab table.
  • Updated parameter names in Parameter Settings: Profile #N (N=0-32) Tab table to match the new names.
  • Added new table Additional Parameter Settings for Secondary Profiles: Profile #N (N=1-32) Tab.
  • Updated parameter names in Configuring the F-Tile PMA/FEC Direct PHY Multirate Intel FPGA IP Core section.
  • Added new topics with examples and updated tables in the Configuration Registers chapter.
2022.04.12 22.1 1.0.0 Initial release.
Level Two Title